1. Field of the Invention
The present invention relates to display apparatuses, and particularly to active-matrix display apparatuses having drive circuits for individual pixels.
2. Description of the Related Art
Flat-panel display apparatuses, typified by liquid crystal displays, can provide a display with high image quality at high response speed by employing an active-matrix structure where drive circuits including thin-film transistors (TFTs) are provided for individual pixels.
FIG. 9A is a partially cutaway schematic plan view of the main part of each pixel on the drive-panel side of a known active-matrix display apparatus, and FIG. 9B is a sectional view taken along line IXB-IXB of FIG. 9A, passing through connection holes. In FIGS. 9A and 9B, each pixel region includes a scanning line 4 extending in one direction, a first interlayer insulating film 11 covering the scanning line 4, and a capacitor Cs disposed on top of the first interlayer insulating film 11. The capacitor Cs includes a lower electrode 12c, a dielectric film 13c, and an upper electrode 14c which are sequentially stacked over the scanning line 4. The capacitor Cs is covered with a second interlayer insulating film 15 on which a signal line 5 is disposed so as to extend in a direction crossing the scanning line 4. Each pixel region corresponds to the intersection of the scanning line 4 and the signal line 5.
A relay electrode 200 connected to the upper electrode 14c of the capacitor Cs is disposed adjacent to the signal line 5 on the second interlayer insulating film 15 such that the relay electrode 200 overlaps the scanning line 4, and another relay line 5c is disposed adjacent to the relay electrode 200. The relay electrode 200 is connected to the upper electrode 14c via a connection hole 201 defined in the second interlayer insulating film 15. The relay electrode 200 is formed in an isolated island pattern so as to be insulated from the signal line 5 and the line 5c. The signal line 5, the relay electrode 200, and the line 5c are covered with a third interlayer insulating film 16 on which a common line 6 is disposed. The common line 6 is connected to the relay electrode 200 and thus the upper electrode 14c of the capacitor Cs via a connection hole 202 defined in the third interlayer insulating film 16. The common line 6 is connected to an electrode disposed on a counter panel in the periphery of the drive panel so that the potential of the upper electrode 14c of the capacitor Cs becomes the common potential. Thus, the common lines 6 are formed in a matrix pattern so as to cover the signal lines 5 and the scanning lines 4 or in a striped pattern so as to be divided between the signal lines 5. The common lines 6 also function as a light-shielding film for blocking light incident on transistors.
Another structure disclosed does not use the relay electrode 200 for connection between the upper electrode 14c of the capacitor Cs and the common line 6. In this structure, the upper electrode 14c of the capacitor Cs is directly connected to the common line 6 via a connection hole continuously penetrating the interlayer insulating films 15 and 16 shown in FIG. 9B. In this case, the aspect ratio of the connection hole, that is, the ratio of depth to width, is adjusted to 1 or less to prevent the inner line formed by sputtering from being discontinuous due to low coverage (see Japanese Unexamined Patent Application Publication No. 2005-222019).